System-on-chip (SOC) devices typically include internal memory for storage of information such as instructions and/or data. Internal memory blocks in an SOC device typically occupies substantial chip area of an integrated circuit (IC) chip that contains the SOC device. For example, internal memory blocks may occupy as much as about 70% of the IC chip area of an SOC device. The configuration of internal memory in SOC devices are generally similar to the configuration of memory in individual memory chips.
Memory blocks of SOC devices and memory chips used as information storage devices traditionally include read only memory (ROM) blocks, which are typically used only for reading, and random access memory (RAM) blocks, which may be written as well as read. RAM blocks typically include static random access memory (SRAM) blocks and dynamic random access memory (DRAM) blocks.
Each block of RAM includes a number of memory cells. Each memory cell typically stores one bit of information. Typical RAM blocks have capacity to store anywhere from thousands to millions of bits of data. Since vast numbers of memory cells are used to store information in RAM blocks, the size of RAM blocks depends, to large extent, on the size of each memory cell.
A conventional memory cell in the RAM block of an SOC device or an SRAM chip is typically made up of six transistors in a 6T configuration. Memory cells in DRAM blocks typically require less number of transistors per bit. For example, some DRAM blocks contain memory cells with one transistor per bit. Therefore, DRAM blocks of SOC devices and DRAM chips are typically smaller than SRAM blocks with similar information storage capacity.
SRAM blocks are generally used for fast memory access. DRAM block accesses typically are not as fast as the SRAM block accesses, and thus for applications that require fast memory accesses, such as graphics cache, SRAM blocks are generally used. SRAM blocks also have an advantage of being able to retain data bits without refreshing since data bits are typically stored in memory cells of the SRAM blocks without much charge leakage.
If a less number of transistors could be used in a RAM cell, which has a comparable speed and data reliability to SRAM cells while maintaining small size of a DRAM cell, a RAM architecture based on such RAM cell could help to reduce the size of many integrated circuit chips and packages, including SOC devices and individual RAM chips.
One embodiment of the present invention is a system-on-chip device that includes a memory block. The memory block includes a memory cell array having a plurality of memory cells organized into rows and columns. Each of the plurality of memory cells in a column is coupled to both a read bit line and a write bit line. The memory block also includes a refresh address generator for generating a refresh address. The refresh address is used to refresh the plurality of memory cells in the memory cell array.
Another embodiment of the present invention is a memory block that includes a memory cell array having a plurality of memory cells organized into rows and columns. Each of the plurality of memory cells in a column is coupled to both a read bit line and a write bit line. The memory block also includes a refresh address generator for generating a refresh address. The refresh address is used to refresh the plurality of memory cells in the memory cell array.
A collision avoidance mechanism is implemented in another embodiment of the present invention. In this embodiment, the memory block includes a comparator. The comparator is used to compare an access address and a refresh address. If the access address is the same as the refresh address. The refresh address is updated using a pre-determined algorithm.
In yet another embodiment of the present invention, an access operation using the access address and a refresh operation using the refresh address are performed substantially simultaneously. The access operation can be used to write to a first memory cell while the refresh operation reads from a second memory cell, which is on the same column as the first memory cell. In addition, the access operation can be used to read from the first memory cell while the refresh operation writes to the second memory cell.
Yet another embodiment of the present invention is a memory cell that includes a first transistor, a second transistor and a third transistor. Each of the three transistors have a gate, a first terminal and a second terminal. The first terminal of the first transistor is coupled to a write bit line. The second terminal of the first transistor is coupled to the gate of the second transistor. The second terminal of the third transistor is coupled to the first terminal of the second transistor. The first terminal of the third transistor is coupled to a read bit line.
Yet another embodiment of the present invention is a method of refreshing a memory cell while performing an access operation. An access address is provided to be used for the access operation. A refresh address is generated for a refresh operation. The access address is compared with the refresh address. If the access address and the refresh address are the same, a pre-determined algorithm is used to update the refresh address.